1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, in particular, to interconnections in integrated circuits.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, which form an electric circuit. In addition to active devices, such as, for example, field effect transistors and/or bipolar transistors, circuit elements provided in integrated circuits may include passive devices such as capacitors, inductivities and/or resistors. The devices are connected internally by means of electrically conductive lines including an electrically conductive material such as, for example, copper. To accommodate all the electrically conductive lines required to connect the circuit elements in modern integrated circuits, the electrically conductive lines may be arranged in a plurality of levels stacked on top of each other. To connect electrically conductive lines provided in different levels, contact vias may be formed in interlayer dielectrics separating the levels from each other. The vias may be filed with an electrically conductive material, which may include a metal such as, for example, copper.
For forming electrically conductive lines and contact vias including an electrically conductive material including copper in a semiconductor structure, the dual damascene technique may be employed.
In the dual damascene technique, contact vias and trenches are formed in an interlayer dielectric. The trenches correspond to the electrically conductive lines. One or more diffusion barrier layers including a diffusion barrier layer material such as, for example, titanium nitride, tantalum and/or tantalum nitride, as well as a layer of the electrically conductive material, for example a layer of copper and/or a copper alloy, are deposited over the semiconductor structure.
Thereafter, a chemical mechanical polishing (CMP) process may be performed. In the CMP process, portions of the one or more diffusion barrier layers and/or the layer of electrically conductive material outside the contact vias and trenches may be removed. Portions of the electrically conductive material in the contact vias and trenches may remain in the semiconductor structure. The trenches filled with the electrically conductive material form electrically conductive lines that connect circuit elements in the semiconductor structure. The contact vias filled with the electrically conductive material provide electrical connections between different layers, as detailed above. The one or more diffusion barrier layers may substantially prevent or at least reduce a diffusion of the electrically conductive material through the interlayer dielectric, which might adversely affect the functionality of the integrated circuit.
For forming the contact vias and trenches in the interlayer dielectric, techniques of photolithography and etching may be employed. Etch processes employed in the formation of contact vias and trenches may include, in particular, dry etch processes, such as reactive ion etching. In such etch processes, the interlayer dielectric may be damaged, in particular when the interlayer dielectric includes a porous low-k or ultra-low-k (ULK) material. Furthermore, etch processes may leave unwanted residuals on surfaces of electrically conductive features provided in lower interconnect levels that are exposed in the etch process.
Residuals on copper surfaces may include polymers and copper oxide. Since the presence of etch residuals on copper surfaces may adversely affect the functionality of an integrated circuit, for example, by increasing RC-delays and/or a likelihood of time dependent dielectric breakdown (TDDB) occurring, it has been proposed to perform one or more cleaning processes after the etching of contact vias and trenches.
Such cleaning processes, however, may have issues associated therewith, which may include modifications of the interlayer dielectric, such as an undesirable increase of the dielectric constant of the interlayer dielectric in the vicinity of its surface and/or its interface with other materials by carbon depletion. Modifications of the interlayer dielectric may lead to RC-delays and even failure of integrated circuits due to time dependent dielectric breakdown.
The present disclosure provides methods wherein the above-mentioned issues may be substantially avoided or at least reduced.